The present invention relates to an oversampling converter for performing A/D or D/A conversion at a clock frequency much higher than a signal frequency.
It is generally known that an original signal can be reproduced according to the Nyquist's theorem at a sampling frequency (f.sub.S), which is set to be about twice a signal frequency bandwidth (f.sub.BD) when an analog signal is sampled or a sampled digital signal is converted to an analog signal. In other words, the sampling frequency (f.sub.S) of general A/D or D/A converters is selected to be about twice the signal frequency bandwidth (f.sub.BW).
In a conventional oversampling A/D or D/A converter, its sampling frequency (f.sub.S) is set to be higher than twice the signal frequency bandwidth (f.sub.BW), to improve conversion precision.
For example, a conversion error of an A/D converter occurs when a sampled analog signal is quantized to a digital signal. This quantization error is the difference between an input voltage and a quantized voltage of a quantizer, and is given as a random value falling within an amplitude range of .+-.V.sub.q /2 with respect to a minimum quantized step voltage (V.sub.q). For this reason, the frequency spectrum of quantization noise generated by quantization errors is uniformly distributed within a bandwidth f.sub.S /2.
Because the total of quantization noise power is determined by the noise amplitude, the higher the sampling frequency (f.sub.S) is, the lower the level of each spectrum is, due to dispersion of noise over a wide range. For example, if quantization noise of 16 KHz or more is filtered out at a signal frequency bandwidth f.sub.BW of 16 KHz and a sampling frequency f.sub.S of 2048 KHz, residual quantization noise power in the signal bandwidth is decreased to 2.multidot.f.sub.BW /f.sub.S =1/64.
When oversampling is performed at a frequency which is 64 times the sampling frequency (f.sub.S), the quantization noise power is decreased to 1/64, so that the S/N ratio can be increased by about 18 dB. This increase in S/N ratio corresponds with the fact that a quantization resolution of the A/D converter is increased by eight times (i.e., 3 bits).
A typical conventional oversampling A/D converter is exemplified by a delta-sigma oversampling A/D converter. The delta-sigma oversampling A/D converters are divided into two types: single integration type converter and a double integration type converter. A single integration type converter is described in IEEE Journal of Solid-State Circuits, August 1981, Vol.-SC-16 No. 4, T. Misawa & J. E. Iwersen, "Single-Chip per Channel Codec with Filters Utilizing .DELTA.-.SIGMA. Modulation" PP. 333-341. This codec has a single integrator, a quantizer for quantizing an output from the integrator, and a negative feedback path for feeding back an output from the quantizer to an input terminal of the integrator. Typical examples of such codecs are shown in FIG. 20A (an A/D converter) and FIG. 20B (a D/A converter).
Referring to FIGS. 20A and 20B, reference numeral 1 denotes a signal input terminal; 2, a signal output terminal; 3, a quantizer; 4, a digital-to-analog converter (to be referred to as a D/A converter hereinafter); 5, an integrator circuit; 5-1, an integrator constituting the integrator circuit; 6, an adder; and 7, a delay circuit inserted between the output terminal of the quantizer 3 and the D/A converter 4. In the circuits in FIGS. 20A and 20B, the integrator circuit 5 distributes a majority of quantization noise components in the high-frequency range, the noise level being low in the low frequency range and high in the high-frequency range. Therefore, the S/N ratio is higher than that in the method of simply increasing the sampling frequency (f.sub.S).
With the above arrangement, a quantizer output V.sub.OUT appearing at the output side 2 of the quantizer 3 is given by the following equation: EQU V.sub.OUT =V.sub.IN .multidot.H.sub.1 /(1+Z.sup.-1 .multidot.H.sub.1)+V.sub.QN /(1+Z.sup.-1 .multidot.H.sub.1) (1)
where V.sub.IN is the input signal supplied to the input terminal 1, H.sub.1 is the transfer function or gain of the integrator, V.sub.q is the quantization noise, Z.sup.-1 =e.sup.j.omega.T, .omega.=2.pi.f, T=1/f.sub.S, and f.sub.S is the sampling frequency.
A signal component of the first term of equation (1) is H.sub.1 /(1+Z.sup.-1 .multidot.H.sub.1).perspectiveto.1 and has substantially flat frequency characteristics. A signal component of the second term defined as V.sub.TN is associated with quantization noise and is given as H.sub.1 =1/(1-Z.sup.-1), so that EQU V.sub.TN =V.sub.qN .multidot.(1-Z.sup.-1) (1')
The equivalent characteristic (1-Z.sup.-1) is given as EQU (1-Z.sup.-1)=1-e.sup.-j.omega.T =2 sin (.pi.f/f.sub.S)
This noise is found to be suppressed when its frequency is decreased through the transfer function H.sub.1 of the integrator. With this arrangement, when only a signal of the signal bandwidth is extracted by a low-pass filter, a signal with a high S/N ratio can be obtained.
In order to convert the obtained digital signal to an analog signal again, a D/A converter 4 is used. Conversion precision of the D/A converter 4 is determined by resolution and linearity. In general, a reference voltage is divided by resistor or capacitor elements in accordance with an input signal to generate an ouput voltage. It is possible to improve the resolution by increasing the number of elements. However, when each output voltage is not accurately linear, a decoded analog voltage is inevitably distorted, analog output linearity depends on the precision of elements constituting the D/A converter, so in order to obtain a high-precision D/A converter, a large number of high-precision elements are required therein.
Conversely, the accurate output analog voltage can be obtained at a low resolution with a binary output (one-bit resolution) and a ternary output (2-bit resolution) without using a plurality of elements. In this case, high-precision linearity can be obtained irrespective of precision of the elements. Since any two points given by binary outputs are plotted on a line, substantially no problems with linearity occur. For ternary outputs, a positive or negative reference voltage is charged by or not charged by a single capacitor element to obtain three voltages of good linearity. Since linearity of a D/A converter with a low resolution of 1 to 2 bits can be quaranteed, high conversion precision can be achieved only if a conversion error occurring at low resolution is decreased.
To achieve this, a D/A converter with a one-bit resolution is used. The basic arrangement of such a D/A converter is given as follows: An input signal is supplied to an integrator, and an output therefrom is quantized by a quantizer, and is then converted by a D/A converter to an analog signal. In this case, the output from the quantizer is negatively fed back to the input side of the integrator, thereby decreasing noise.
In order to obtain higher conversion precision than the single integration type delta-sigma oversampling converter, a double integration type delta-sigma oversampling converter has been proposed. A typical example of this type of converter is described in U.S. Pat. No. 4,439,756. Double integration type delta-sigma converters are exemplified in FIG. 21A (an A/D converter) and FIG. 21B (a D/A converter). With the given arrangements, when a transfer function of an additional integrator is given as H.sub.2, and other arrangements are the same as those of the single integration type converter in FIG. 20A, B, a quantized output V.sub.OUT is given as follows: EQU V.sub.OUT =V.sub.IN .multidot.H.sub.1 .multidot.H.sub.2 /(1+Z.sup.-1 .multidot.H.sub.1 .multidot.H.sub.2 +Z.sup.-1 .multidot.H.sub.2)+V.sub.q /(1+Z.sup.-1 .multidot.H.sub.1 .multidot.H.sub.2 +Z.sup.-1 .multidot.H.sub.2) (2)
The second term; total noise of converter, V.sub.TN is given: EQU V.sub.TN =V.sub.qN .multidot.(1-Z.sup.-1).sup.2 ( 2')
for H.sub.1 =H.sub.2 =1/(1-Z.sup.-1).
As is apparent from the second term in equation (2), the noise components of the quantizer are greatly decreased from those of the single integration type delta-sigma converter.
A converter for improving an S/N ratio by changing the noise frequency distribution characteristics is called a noise shaping type converter. More particularly, in the converters in FIGS. 20A and 20B, if f.sub.BW =16 kHz and f.sub.S =2048 kHz, the noise level within the bandwidth is attenuated by about 31 dB in accordance with equation (1'). In addition to an increase (i.e., 18 dB) in S/N ratio due to dispersion of quantization noise components over a wide range, as described above, a total increase in S/N ratio in the circuits of FIGS. 20A and 20B can be about 49 dB.
In the circuit arrangements in FIGS. 20A and 20B and FIGS. 21A and 21B, the integrators 5-1, 5-2, and 5-4 are normally constituted by operational amplifiers which have an operation speed lower than that of the quantizer 3 and the D/A converter 4. For this reason, the operation speed of the integrators substantially determines the upper limit of the sampling frequency (f.sub.S). Each arrangement in FIGS. 21A and 21B has two integrators connected in series and requires processing time twice that of the arrangements in FIGS. 20A and 20B, so that the upper limit of the sampling frequency (f.sub.S) is about 1/2 that of the FIG. 2 or 20. Even if the S/N ratio is increased by a series circuit of integrators, the total effect is not increased much.
More specifically, when an increase in S/N ratio in each arrangement of FIGS. 21A and 21B at f.sub.BW =16 kHz and f.sub.S =1024 kHz is calculated, an S/N ratio increase component by dispersion of the quantization noise components over the wide range is about 15 dB, and an S/N ratio increase component by noise shaping is about 47 dB according to equation (2'), the total increase in S/N ratio is 62 dB. Since the increase in S/N ratio in each arrangement in FIGS. 20A and 20B is only 49 dB, the S/N ratio of each arrangement in FIGS. 21A and 21B is increased thereover by 13 dB.
If a resolution of the quantizer is N.sub.q bits and a signal voltage range is .+-.1 V, an average value of a square V.sub.qN.sup.2 of the quantization error is (2.sup.2-N.sub.q).sup.2 /12, and an average voltage of a sinusoidal wave of peak level is 1/.sqroot.2. Therefore, its S/N ratio is given as 10 log (6/(2.sup.2-N.sub.q).sup.2) (dB). The S/N ratio of only the quantizer is given as 6.times.(N.sub.q -1)+1.8 (dB). In the arrangement of FIG. 21B, an increase in S/N ratio is 62 dB (f.sub.BW =16 kHz and f.sub.S = 1024 kHz). When the quantizer has a 2-bit resolution (ternary output for the D/A converter), an S/N ratio is 69.8 dB, as a sum of 7.8 dB of the quantizer and the already improved 62 dB.
However, when the additional integrator is used, the possibility of loop oscillation is high. In order to quarantee operation stability, a phase lead bypath must be arranged. When a triple or more integration type converter is used, loop oscillation inevitably occurs.
In addition, when at least two integrators are cascade-connected to constitute a feedback loop, processing time is at least doubled, and the sampling frequency is decreased. With such an arrangement, when an input signal level is high, the loop becomes unstable. As a result, the S/N ratio is decreased.
On the contrary, in order to obtain a high integrator gain with a single integrator, an amplifier with a high gain is required. In this case, wide bandwidth cannot be used, and the sampling frequency (f.sub.S) cannot be increased.
In short, when the number of integrators is increased, high conversion precision cannot be obtained in conventional delta-sigma oversampling converters.